jfet input operational amplifiers these lowcost jfet input operational amplifiers combine two stateof theart linear technologies on a single monolithic integrated circuit. each internally compensated operational amplifier has well matched high voltage jfet input devices for low input offset voltage. the bifet technology provides wide bandwidths and fast slew rates with low input bias currents, input offset currents, and supply currents. these devices are available in single, dual and quad operational amplifiers which are pincompatible with the industry standard mc1741, mc1458, and the mc3403/lm324 bipolar products. ? input offset voltage options of 6.0 mv and 15 mv max ? low input bias current: 30 pa ? low input offset current: 5.0 pa ? wide gain bandwidth: 4.0 mhz ? high slew rate: 13 v/ m s ? low supply current: 1.4 ma per amplifier ? high input impedance: 10 12 w ordering information op amp function device operating temperature range package single tl081cd t 0 to +70 c so8 single tl081acp t a = 0 to +70 c plastic dip dual tl082cd t 0 to +70 c so8 dual tl082acp t a = 0 to +70 c plastic dip quad tl084cn, acn t a = 0 to +70 c plastic dip on semiconductor ? semiconductor components industries, llc, 2002 march, 2002 rev. 2 1 publication order number: tl081c/d tl081c,ac tl082c,ac tl084c,ac semiconductor technical data jfet input operational amplifiers tl081 (top view) tl082 (top view) d suffix plastic package case 751 (so8) p suffix plastic package case 626 1 1 8 8 pin connections + offset null noninvt input v ee inv + input v ee inputs a output a nc v cc output offset null inputs b output b v cc + + 18 7 6 5 2 3 4 18 7 6 5 2 3 4 tl084 (top view) n suffix plastic package case 646 pin connections 4 23 1 14 1 inputs 1 output 1 v cc inputs 2 output 2 output 4 inputs 4 v ee inputs 3 output 3 + + ++ 114 13 12 11 10 9 8 2 3 4 5 6 7 representative circuit schematic (each amplifier) - + inputs q3 q4 q5 q2 q1 v cc q6 j1 j2 q17 q20 q23 24 j3 2.0 k q14 q15 10 pf q19 q21 q22 q24 q9 q8 q7 q25 q12 q10 q13 q11 q16 q18 1.5k v ee bias circuitry common to all amplifiers offset null (tl081 only) output 1.5k
tl081c,ac tl082c,ac tl084c,ac http://onsemi.com 2 maximum ratings rating symbol value unit supply voltage v cc 18 v v ee 18 differential input voltage v id 30 v input voltage range (note 1) v idr 15 v output short circuit duration (note 2) t sc continuous power dissipation plastic package (n, p) p d 680 mw derate above t a = +47 c 1/ q ja 10 mw/ c operating ambient temperature range t a 0 to +70 c storage temperature range t stg 65 to +150 c notes: 1. the magnitude of the input voltage must not exceed the magnitude of the supply voltage or 15 v, whichever is less. 2. the output may be shorted to ground or either supply. temperature and/or supply voltages must be limited to ensure that power dissipation ratings are not exceeded. 3. esd data available upon request. electrical characteristics (v cc = 15 v, v ee = 15 v, t a = t low to t high [note 1].) characteristics symbol min typ max unit input offset voltage (r s 10 k, v cm = 0) v io mv tl081c, tl082c 20 tl084c 20 tl08_ac 7.5 input offset current (v cm = 0) (note 2) i io na tl08_c 5.0 tl08_ac 3.0 input bias current (v cm = 0) (note 2) i ib na tl08_c 10 tl08_ac 7.0 largesignal voltage gain (v o = 10 v,r l 2.0 k) a vol v/mv tl08_c 15 tl08_ac 25 output voltage swing (peaktopeak) v o v (r l 10 k) 24 (r l 2.0 k) 20 notes: 1. t low =0 c for tl081ac,c t high =70 c for tl081ac 0 c for tl082ac,c +70 c for tl082ac,c 0 c for tl084ac,c +70 c for tl084ac,c 2. input bias currents of jfet input op amps approximately double for every 10 c rise in junction temperature as shown in figure 3. to maintain junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing. figure 1. unity gain voltage follower figure 2. inverting gain of 10 amplifier - + v in r l = 2.0 k v o c l = 100 pf - + v in r l v o c l = 100 pf 10 k 1.0 k
tl081c,ac tl082c,ac tl084c,ac http://onsemi.com 3 electrical characteristics (v cc = 15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics symbol min typ max unit input offset voltage (r s 10 k, v cm = 0) v io mv tl081c, tl082c 5.0 15 tl084c 5.0 15 tl08_ac 3.0 6.0 average temperature coefficient of input offset voltage d v io / d t 10 m v/ c r s = 50 w , t a = t low to t high (note 1) input offset current (v cm = 0) (note 2) i io pa tl08_c 5.0 200 tl08_ac 5.0 100 input bias current (v cm = 0) (note 2) i ib pa tl08_c 30 400 tl08_ac 30 200 input resistance r i 10 12 w common mode input voltage range v icr v tl08_c 10 15, 12 tl08_ac 11 15, 12 large signal voltage gain (v o = 10 v, r l 2.0 k) a vol v/mv tl08_c 25 150 tl08_ac 50 150 output voltage swing (peaktopeak) v o 24 28 v (r l = 10 k) common mode rejection ratio (r s 10 k) cmrr db tl08_c 70 100 tl08_ac 80 100 supply voltage rejection ratio (r s 10 k) psrr db tl08_c 70 100 tl08_ac 80 100 supply current (each amplifier) i d 1.4 2.8 ma unity gain bandwidth bw 4.0 mhz slew rate (see figure 1) sr 13 v/ m s v in = 10 v, r l = 2.0 k, c l = 100 pf rise time (see figure 1) t r 0.1 m s overshoot (v in = 20 mv, r l = 2.0 k, c l = 100 pf) os 10 % equivalent input noise voltage e n 25 nv/ hz r s = 100 w , f = 1000 hz channel separation cs 120 db a v = 100 notes: 1. t low =0 c for tl081ac,c t high =70 c for tl081ac 0 c for tl082ac,c +70 c for tl082ac,c 0 c for tl084ac,c +70 c for tl084ac,c 2. input bias currents of jfet input op amps approximately double for every 10 c rise in junction temperature as shown in figure 3. to maintain junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing.
tl081c,ac tl082c,ac tl084c,ac http://onsemi.com 4 v o , output voltage swing (v pp ) v o , output voltage swing (v pp ) v o , output voltage swing (v pp ) v o , output voltage swing (v pp ) v cc /v ee = 15 v (see figure 2) r l = 10 k r l = 2.0 k figure 3. input bias current versus temperature figure 4. output voltage swing versus frequency figure 5. output voltage swing versus load resistance figure 6. output voltage swing versus supply voltage figure 7. output voltage swing versus temperature figure 8. supply current per amplifier versus temperature t a , ambient temperature ( c) ib -75 -50 -25 0 25 50 75 100 125 v cc /v ee = 15 v 100 1.0 k 10 k 100 k 1.0 m 10 m f, frequency (hz) r l , load resistance (k w ) 0.1 0.2 0.4 0.7 1.0 2.0 10 4.0 7.0 v cc , |v ee | , supply voltage ( v) 0 5.0 10 15 20 r l = 2.0 k t a = 25 c t a , ambient temperature ( c) -50 -25 0 25 50 75 100 125 t a , ambient temperature ( c) -50 -25 0 25 50 75 100 125 i d v cc /v ee = 15 v t a = 25 c (see figure 2) 0.6 100 10 1.0 0.1 0.01 30 25 20 15 10 5.0 0 30 20 10 5.0 0 40 30 20 10 0 35 30 25 20 15 10 5.0 0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.4 0.2 0 v cc /v ee = 15 v 10 v 5.0 v r l = 2.0 k t a = 25 c (see figure 2) v cc /v ee = 15 v i , input bias current (na) , supply drain current (ma) -100 150 35 40 40 -75 -75
tl081c,ac tl082c,ac tl084c,ac http://onsemi.com 5 , open-loop gain (v/m/v) vol a , equivalent input noise voltage ( figure 9. large signal voltage gain and phase shift versus frequency figure 10. large signal voltage gain versus temperature figure 11. normalized slew rate versus temperature figure 12. equivalent input noise voltage versus frequency figure 13. total harmonic distortion versus frequency f, frequency (hz) phase shift (degrees) 10 6 10 5 10 4 10 3 10 1 10 2 1.0 1.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m , open-loop gain (v/m/v) vol gain phase shift v cc /v ee = 15 v r l = 2.0 k t a = 25 c v cc /v ee = 15 v v o = 10 v r l = 2.0 k t a , ambient temperature ( c) 1000 100 10 1.0 -50 -25 0 25 50 75 100 125 t a , ambient temperature ( c) normalized slew rate 1.15 1.10 1.05 1.0 0.95 0.90 0.85 -50 -25 0 25 50 75 100 125 f, frequency (hz) 60 50 40 30 20 10 0 0.01 0.05 0.1 0.5 1.0 5.0 10 50 100 v cc /v ee = 15 v a v = 10 r s = 100 w t a = 25 c v cc /v ee = 15 v a v = 1.0 v o = 6.0 v (rms) t a = 25 c f, frequency (hz) thd, total harmonic distortion (%) 1.0 0.5 0.1 0.05 0.01 0.005 0.001 0.1 0.5 1.0 5.0 10 50 100 0 45 90 135 180 a e nv/ hz n ) 10 7 10 8 100 m -75 -100 150 1.20 0.80 -75 70
tl081c,ac tl082c,ac tl084c,ac http://onsemi.com 6 - + - + reset v in 1/2 tl082 1n914 1.0 m f * *polycarbonate or polystyrene capacitor v o figure 14. positive peak detector v r run r4 r1 v1 r3 tl081 6 r6 clear c* r5 - + *polycarbonate or polystyrene capacitor time (t) = r4 c n (v r /v r -v i ), r 3 = r 4 , r 5 = 0.1 r 6 if r1 = r2: t = 0.693 r4c design example: 100 second timer v r = 10 v c = l.0 mf r3 = r4 = 144 m r6 = 20 k r5 = 2.0 k r1 = r2 = 1.0 k r2 figure 15. voltage controlled current source figure 16. long interval rc timer r2 5.1 k v o r1 5.1 k tl081 r l 5.1 k c l 0.5 m f c c 20 pf r3 10 2.0 v 0 v/ m s = 0.04 v/ m s (with c l shown) ? overshoot 10% ? t s = 10 m s ? when driving large c l , the v o slew rate is determined by c l ? and i o(max) : -2.0 v i o figure 17. isolating large capacitive loads if r1 through r4 > > r5 then i out = + v in r1 r5 r2 tl081 r4 i o - 1/2 tl082 - + v in r5 v o t i o c l 0.02 0.5 r3
tl081c,ac tl082c,ac tl084c,ac http://onsemi.com 7 outline dimensions p suffix plastic package case 62605 issue k 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 d suffix plastic package case 75105 (so8) issue s seating plane 1 4 5 8 a 0.25 m cb ss 0.25 m b m h c x 45 l dim min max millimeters a 1.35 1.75 a1 0.10 0.25 b 0.35 0.49 c 0.18 0.25 d 4.80 5.00 e 1.27 bsc e 3.80 4.00 h 5.80 6.20 h 0 7 l 0.40 1.25 0.25 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions are in millimeters. 3. dimension d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include mold protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. d e h a b e b a1 c a 0.10
tl081c,ac tl082c,ac tl084c,ac http://onsemi.com 8 outline dimensions n suffix plastic package case 64606 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n t 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. tl081c/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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